As an example of our technical ability, in this case in the field of software engineering for transport but it can also apply to many other areas, on a recent project we used an IDT 519EE901 device as the solution to generating a selection of low clock rates from a single oscillator – giving us a high reliability set of clock frequencies in the range 62.5 to 66.725 KHz. Most of the readily available generators are great in the Megahertz range not so good below. A bit of research came up with the IDT 519EE901 device which the manufacturers describe as:
The IDT 5V19EE901 is a programmable clock generator intended for high performance data-communications, telecommunications, consumer, and networking applications. There are four internal PLLs, each individually programmable, allowing for four unique non-integer-related frequencies. The frequencies are generated from a single reference clock. The reference clock can come from one of the two redundant clock inputs. Automatic or manual switchover function allows any one of the redundant clocks to be selected during normal operation. The 5V19EE901 is in-system, programmable and can be programmed through the use of I2C interface. An internal EEPROM allows the user to save and restore the configuration of the device without having to reprogram it on power-up. Each of the four PLLs has an 7-bit reference divider and a 12-bit feedback divider. This allows the user to generate four unique non-integer-related frequencies. The PLL loop bandwidth is programmable to allow the user to tailor the PLL response to the application. For instance, the user can tune the PLL parameters to minimize jitter generation or to maximize jitter attenuation. Spread spectrum generation and/or fractional divides are allowed on two of the PLLs. There are a total of six 8-bit output dividers. Each output bank can be configured to support LVTTL, LVPECL, LVDS or HCSL logic levels. Out0 (Output 0) supports 3.3V single ended output only. The outputs are connected to the PLLs via a switch matrix. The switch matrix allows the user to route the PLL outputs to any output bank. This feature can be used to simplify and optimize the board layout. In addition, each output’s slew rate and enable/disable function is programmable.
The problem was that we couldn’t get the outputs to work. We read everything we could find on the device but none of it helped. The secret is that the initial PLL outputs have to operate in the range of 100 MHz to 1.2 GHz. You can then use multiple dividers to get the lower frequencies from these. Once your PLLs are operating over 100 MHz, everything on the site is correct. We are now happily using this product.
The easiest way to get the correct register settings is definitely to use IDT’s Versaclock configuration program and then export the register values. The export takes the form of an easy to manipulate text file, that can be imported into excel, or directly into your programs.
